The present invention pertains to reducing average power consumption by a computer system. More particularly, the invention pertains to selecting between various modes of operation in a computer system having a hub interface architecture.
Prior computer systems typically rely on standardized busses, such as the Peripheral Component Interconnect (PCI) bus adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland Oregon, to allow computer system chipset components to communicate one with another. For example, a transaction originating at a processor and intended for a disk drive might first be delivered to a first chipset component that serves as an intermediary between the processor bus and a PCI bus. The first chipset component would then deliver the transaction over the PCI bus to a second system chipset component which would then deliver the transaction to the disk drive.
Busses such as the PCI bus also provide for communication with other computer system devices such as graphics controllers and network adapters. Because busses such as the PCI bus must interface with a variety of component types, each with varying requirements, the busses are not necessarily optimized for allowing communication between chipset components. Further, chipset manufacturers who rely on standardized busses such as the PCI bus must adhere to bus standards in order to ensure compatibility with other components, and are not at liberty to make substantial changes in how the chipset components communicate with each other.
Another issue that faces chipset component manufacturers in designing and manufacturing chipset components is the need to conform to standardized supply and signaling voltages when relying on busses such as PCI for communication between chipset components, thereby locking the manufacturers into certain design practices and manufacturing technologies. Therefore, it would be desirable to provide a flexible interface that provides optimal communication between chipset components. In addition, it would be desirable to provide a method and apparatus for selecting between various modes of operation in chipset components coupled to such an interface.
A method of selecting data clocking rates in a computer system is disclosed. According to one embodiment, the method includes detecting a reset signal indicating a power-on reset at a first device and a second device, exchanging the data clocking rate capabilities between the first and second devices via a first bus, and operating the first and second devices at a first data clocking rate. The first data clocking rate corresponds to the highest data clocking rate supported by the first and second devices